FPGA GPIO

When I have some spare time, I am still playing with my FPGA board, meanwhile I went through some on line training graciously offered by Altera and also some documents they make available on the web.

Wow, there is A LOT of valuable information available there, thanks Altera!

Fact is that FPGAs are incredibly flexible devices and with flexibility often you get complexity.

To be fair Quartus II partially helps out in dealing with such complexity, provided you are used to the complexity of an Eclipse interface at least!
That said, I must admit it is easy to get lost in the rich menus of the IDE, so I decided to investigate deeper one thing at a time.

A good starting point seemed to be the I/O section.

When, in Verilog, you define a module such as

module pong(clk, vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B, quadA, quadB);
input clk;
output vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B;
input quadA, quadB;

you can place it in the schematic design and verify that it has certain inputs and outputs (as defined in your module declaration)

Those inputs and outputs could be connected to other modules in your design, or they could be routed to connect to the external world (like in my example).
In the latter case, you need to attach them to input or output pins.

Once that is done, you still need to tell Quartus to which physical pins they (the input/output signals you defined) have to be connected on your device.

Turns out this is quite an easy task, in fact once you run the Processing-> Start-> Start Alaysis & Elaboration process, these signals become visible for the Pin Planner tool

The Pin Planner is one of the MANY tools/wizards you will have to deal with in Quartus II, it will allow you to perform two important functions :
1) You can assign your signals (nodes) to specific pins, this is quite straightforward, you have the list of nodes on the left and select the " Location " being the pin you would like to connect.
2) You specify the electrical configuration for your pin (actually for your I/O bank)

The I/O banks are similar to the GPIO ports in microcontrollers.
Typically in an MCU a GPIO port has 8 pins, an FPGA I/O Bank typically has more than that and the device I am using has 8 banks.
Now, one incredibly interesting thing is that FPGAs allow you to configure a bank with different Voltages (might vary depending on the device you are using) allowing you to interface external devices operating at different voltages!

However your settings must be homogeneous within the I/O bank, so you cannot have one pin at 2.5V and another one at 1.8V in the same bank, Quartus would complain about that.
To check your settings are consistent you can run the Processing -> Start - Start I/O assignment Analysis process.

Also the current strength can be configured in the same way :

You would imagine that's the place where you can also set an internal pull-up resistor for your inputs... but nope (according to the docs I found), that's  in the Assignment Editor

...where you can set a ton of parameters, for most of which I have no clue at all, cannot even imagine what they are for.
You can specify more than one parameter for the same Node, however some combinations of parameters are not valid, i.e. you cannot enable a weak pullup and define the pin as differential input (yup, also that!) at the same time.

So, long story short, I/O signals in an FPGA can be way more flexible than those on a MCU, you could probably use an FPGA as an extremely expensive logic level translator!